ATA8741-PXQW【PDF 26/238 页】MCU W/TRANSMITTER ASK/FSK 24QFN

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Sheet目录52

22页 23页 24页 25页 [26页]27页 28页 29页 30页

9140CINDCO02/10

ATA8741

12.5 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve

the required performance and flexibility, the following input/output schemes are supported by the

" One 8-bit output operand and one 8-bit result input

" Two 8-bit output operands and one 8-bit result input

" Two 8-bit output operands and one 16-bit result input

" One 16-bit output operand and one 16-bit result input

Figure 12-2 on page 26 shows the structure of the 32 general purpose working registers in the

CPU.

Figure 12-2. AVR CPU General Purpose Working Registers

Most of the instructions operating on the Register File have direct access to all registers, and

most of them are single cycle instructions.

As shown in Figure 12-2, each register is also assigned a Data memory address, mapping them

directly into the first 32 locations of the user Data Space. Although not being physically imple-

mented as SRAM locations, this memory organization provides great flexibility in access of the

registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

12.5.1

The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These reg-

isters are 16-bit address pointers for indirect addressing of the data space. The three indirect

address registers X, Y, and Z are defined as described in Figure 12-3 on page 27.

Addr.

0x00

0x01

0x02

R13

0x0D

General

R14

0x0E

Purpose

R15

0x0F

Working

R16

0x10

Registers

R17

0x11

R26

0x1A

X-register Low Byte

R27

0x1B

X-register High Byte

R28

0x1C

Y-register Low Byte

R29

0x1D

Y-register High Byte

R30

0x1E

Z-register Low Byte

R31

0x1F

Z-register High Byte

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